Smart Serial Bandwidth

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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    put the clock rate 200000 command on the serial int or swap the cable to 0/0/0 so we have a dce. then run the show controller command again.
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    clock rate set to 2000000....out put from sh controller command

    ........................
    Interface Serial0/0/1
    Hardware is GT96K
    DTE Unknown (13)idb at 0x42F54B88, driver data structure at 0x42F5C2A4
    wic_info 0x42F5C8A0
    Physical Port 0, SCC Num 0
    MPSC Registers:
    MMCR_L=0x000304C0, MMCR_H=0x00000000, MPCR=0x00000100
    CHR1=0x00FE007E, CHR2=0x00000000, CHR3=0x00000648, CHR4=0x00000000
    CHR5=0x00000000, CHR6=0x00000000, CHR7=0x00000000, CHR8=0x00000000
    CHR9=0x00000000, CHR10=0x00001828
    SDMA Registers:
    SDC=0x00002201, SDCM=0x00000080
    CRDP=0x0F844C40, CTDP=0x0F8600C0, FTDB=0x0F8600C0
    Main Routing Register=0x77770000 BRG Conf Register=0x00490018
    Rx Clk Routing Register=0x00008888 Tx Clk Routing Register=0x00003219
    GPP Registers:
    Conf=0x50055600, Io=0x50055600, Data=0xEBFFFFFB, Level=0x08000018
    TDM FPGA Registers:
    vmcr[0] = 0x00034080, vmcr[1] = 0x000380C0,
    vmcr[2] = 0x00000000, vmcr[3] = 0x00000000
    ntrcr0 = 0x00000000, ntrcr1 = 0x00000000
    tdmcr = 0x0000006A, labcr = 0x00000000, tpllr_cr = 0x00000000
    nhr = 0x66667007, isr = 0x00000000, imr = 0x000000040 input aborts on receiving flag sequence
    0 throttles, 0 enables
    0 overruns
    0 transmitter underruns
    0 transmitter CTS losts
    0 rxintr, 602 txintr, 0 rxerr, 0 txerr
    252029 mpsc_rx, 0 mpsc_rxerr, 251862 mpsc_rlsc, 167 mpsc_rhnt, 0 mpsc_rfsc
    333 mpsc_rcsc, 0 mpsc_rovr, 0 mpsc_rcdl, 0 mpsc_rckg, 0 mpsc_bper
    0 mpsc_txerr, 766 mpsc_teidl, 0 mpsc_tudr, 0 mpsc_tctsl, 0 mpsc_tckg
    0 sdma_rx_sf, 0 sdma_rx_mfl, 0 sdma_rx_or, 0 sdma_rx_abr, 0 sdma_rx_no
    0 sdma_rx_de, 0 sdma_rx_cdl, 0 sdma_rx_ce, 0 sdma_tx_rl, 0 sdma_tx_ur, 0 sdma_tx
    _ctsl
    0 sdma_rx_reserr, 0 sdma_tx_reserr
    0 rx_bogus_pkts, rx_bogus_flag FALSE
    0 sdma_tx_ur_processed

    tx_limited = 1(2), errata19 count1 - 0, count2 - 0
    Receive Ring
    rxr head (0)(0x0F844C40), rxr tail (0)(0x0F844C40)
    rmd(F844C40): nbd F844C50 cmd_sts 80800000 buf_sz 06000000 buf_ptr F860960
    rmd(F844C50): nbd F844C60 cmd_sts 80800000 buf_sz 06000000 buf_ptr F860FC0
    rmd(F844C60): nbd F844C70 cmd_sts 80800000 buf_sz 06000000 buf_ptr F861620
    rmd(F844C70): nbd F844C80 cmd_sts 80800000 buf_sz 06000000 buf_ptr F861C80
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    Ok. Can you do the same but for the 64k line (don't forget to remove the clock rate)
    twitter: @astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    should i connect the 64k line to the same serial 0/0/1 interface and remove the 512k link??
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    whatever works, i just want to compare the show controllers
    twitter: @astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    this is the 64k link with hdlc encapsulation and no clock rate...
    Interface Serial0/0/1
    Hardware is GT96K
    DTE Unknown (13)idb at 0x42F54B88, driver data structure at 0x42F5C2A4
    wic_info 0x42F5C8A0
    Physical Port 0, SCC Num 0
    MPSC Registers:
    MMCR_L=0x000304C0, MMCR_H=0x00000000, MPCR=0x00000100
    CHR1=0x00FE007E, CHR2=0x00000000, CHR3=0x00000648, CHR4=0x00000000
    CHR5=0x00000000, CHR6=0x00000000, CHR7=0x00000000, CHR8=0x00000000
    CHR9=0x00000000, CHR10=0x00003008
    SDMA Registers:
    SDC=0x00002201, SDCM=0x00000080
    CRDP=0x0F844CD0, CTDP=0x0F860170, FTDB=0x0F860170
    Main Routing Register=0x77770000 BRG Conf Register=0x00490018
    Rx Clk Routing Register=0x00008888 Tx Clk Routing Register=0x00003299
    GPP Registers:
    Conf=0x50055600, Io=0x50055600, Data=0xEBFFFBFB, Level=0x08001818
    TDM FPGA Registers:
    vmcr[0] = 0x00034040, vmcr[1] = 0x000380C0,
    vmcr[2] = 0x00000000, vmcr[3] = 0x00000000
    ntrcr0 = 0x00000000, ntrcr1 = 0x00000000
    tdmcr = 0x0000006A, labcr = 0x00000000, tpllr_cr = 0x00000000
    nhr = 0x66667000, isr = 0x00000303, imr = 0x000000040 input aborts on receiving flag sequence
    0 throttles, 0 enables
    0 overruns
    0 transmitter underruns
    0 transmitter CTS losts
    51 rxintr, 1011 txintr, 0 rxerr, 0 txerr
    379415 mpsc_rx, 0 mpsc_rxerr, 379006 mpsc_rlsc, 278 mpsc_rhnt, 115 mpsc_rfsc
    538 mpsc_rcsc, 0 mpsc_rovr, 0 mpsc_rcdl, 0 mpsc_rckg, 0 mpsc_bper
    0 mpsc_txerr, 1274 mpsc_teidl, 0 mpsc_tudr, 0 mpsc_tctsl, 0 mpsc_tckg
    0 sdma_rx_sf, 0 sdma_rx_mfl, 0 sdma_rx_or, 0 sdma_rx_abr, 0 sdma_rx_no
    0 sdma_rx_de, 0 sdma_rx_cdl, 0 sdma_rx_ce, 0 sdma_tx_rl, 0 sdma_tx_ur, 0 sdma_tx
    _ctsl
    0 sdma_rx_reserr, 0 sdma_tx_reserr
    0 rx_bogus_pkts, rx_bogus_flag FALSE
    0 sdma_tx_ur_processed

    tx_limited = 1(2), errata19 count1 - 0, count2 - 0
    Receive Ring
    rxr head (1)(0x0F844C50), rxr tail (0)(0x0F844C40)
    rmd(F844C40): nbd F844C50 cmd_sts 80800000 buf_sz 06000000 buf_ptr F86CF00
    rmd(F844C50): nbd F844C60 cmd_sts 80800000 buf_sz 06000000 buf_ptr F861620
    rmd(F844C60): nbd F844C70 cmd_sts 80800000 buf_sz 06000000 buf_ptr F860960
    rmd(F844C70): nbd F844C80 cmd_sts 80800000 buf_sz 06000000 buf_ptr F86D560
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    but that one is working right?
    twitter: @astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    yes, this one is working perfectly.
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    Okay, I'm afraid I'm going to have to throw in the towel here, I'm way too rusty on Cisco these days hopefully someone else with a clear head can look at this and the problem will jump out at them. I'll forward this to some of our networking guys and see what they have to offer.

    Sorry I was really hoping we could get this up and running tonight.
    twitter: @astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    yeah, i was looking for a possible solution to this issue....but anyways,thanks for the valuable assistance offered to an amateur like me in the cisco field....it is much appreciated....

    have to keep on looking/digging around till i can find a solution to this issue....hope one of ur network team could assist me further...

    God Bless!!
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    From what it looks like (and according to others) you need to make sure the Alcatel is set for 64k channels and that one of them is providing the clocking for the line. I think you're going to need to call whoever provided the HDSL CSU/DSU's and ask them for config info.
    twitter: @astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    i have reqeuested that information from Telecom. Should be available soon.
    Ben
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  • astorrsastorrs Member Posts: 3,139 ■■■■■■□□□□
    Great, post whatever they give you and we should be able to get this sorted out.
    twitter: @astorrs
    profile: linkedin.com/in/astorrs
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  • penipeni Member Posts: 22 ■□□□□□□□□□
    I have spoken to Telecom staff and they have mentioned that our local gateway provider to the internet provides clocking for the modems (?????????) and that they do not set clock rates on the modems for leased circuits....he mentioned that this was to keep their network "in sync".....
    Ben
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