Why is PCIe a SERIAL expansion bus (instead of a PARALLEL one)?

I ask because, to me, the concept of lanes seems like a way to transfer data in parallel, since based on my research, it seems to me that data is being transferred in each lane at the same time.

What is wrong with my thinking?

Any input would be greatly appreciated!

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Comments

wd40

I am not an expert but I took a quick look in wikipedia.

PCI Express - Wikipedia, the free encyclopedia

If you look at PCI Express connector pinout (×1, ×4, ×8 and ×16 variants)

you will see that an x1 card has only 1 Lane, hence it is serial.

gespenstern

Overall, parallel is a thing of the past. Reason: too many wires, too many connections, too much interference. Bus width grows all the time and in order to support 64-bit transfers on higher speeds it would require more engineering efforts to be made (PCI-X does that).

Serial, on the other hand, was overlooked in the past because there were not enough microprocessors to serialize and multiplex data on both sides of the lane and they were pricey. Nowadays they are cheap and potent. So it's easier and cheaper put on several wires and two multiplexers on both end to encode/decode data than put a freaking number of wires and care about interference on higher frequencies. Plus miniaturization plays a role.

It's a kinda global trend.

s3a

Thanks for the responses.

Gespenstern, is what wd40 implied correct?

In other words, is it the case that a PCIe x1 expansion bus is a serial (so not parallel) expansion bus, but a xk PCIe expansion bus is a parallel (so not serial) expansion bus, where k is an integer 2^n, where n is a positive integer?

Something seems off with such an explanation, though, since what I read online seems to imply that all PCIe expansion busses, regardless of the amount of lanes, are considered to be serial expansion busses.

Basically, my confusion is and was: Why is the transfer of data via a multitude of lanes considered to be serial and not parallel?

I was not asking why serial data transfer is preferred over parallel data transfer.

wd40

You are over thinking it, 16 serial lanes will not make a parallel lane, you still have 16 serial lanes hence the name PCIe x16.

it is all about the technology that drives the Lanes that make them parallel or serial.

Again, read the wikipedia article in full then ask here if it is still not clear.

gespenstern

s3a wrote: »

In other words, is it the case that a PCIe x1 expansion bus is a serial (so not parallel) expansion bus, but a xk PCIe expansion bus is a parallel

It's a catch or wording. It is called serial because data bits get serialized before they are put onto lane. However, when/if we use several lanes the whole situation comes as serial lanes are used in parallel. Say, you want to transfer a two qword from here to there over a x4 PCIe bus. Then every double word gets serialized (i.e. 32 bits of data aren't sent simultaneously in parallel over 32-bit wide data bus, i.e. 32 physical wires, but instead get serialized and transfered over two physical wires still comprising 32-bit wide data bus) and released onto its own lane, thus, each single lane out of total 4 gets its chunk of data and transfers it to the other end. So yeah, each lane is serial, but if we use more than one, then serial lanes work together in parallel and have to get synchronized and timed and all the stuff that is regular for parallel connections.

Compare it to legacy PCI or PCI-X, for example. Data bus here is just a bunch of wires and number of wires comprising a data bus (there are lot of other wires needed, say, for address bus, all the types of control signals, etc) is equal to a data bus width. Say, 32-bit PCI requires 32 wires to transfer 32 bits of data at a time, 64-bit PCI-X requires 64 wires to transfer 64 bits of data at a time and thus the same amount of data can be sent as twice as faster over it. Each data bus wire has its number from 0 to 63 and they are used simultaneously, as is, without any additional manipulation/compression/serialization in transit, see its pinout, so there's no additional chips needed, just wires.

P.S. Let me put it this way, serial and parallel here relate to different concepts. Bits get serialized. But chunks of data bigger than 32 bit, such as qwords, are split in dwords and sent in parallel. Not bits travel over the bus in parallel, but dwords.

s3a

Thanks!

P.S.
For what it's worth, the exact answer I was looking for was:"Bits get serialized. But chunks of data bigger than 32 bit, such as qwords, are split in dwords and sent in parallel. Not bits travel over the bus in parallel, but dwords."

gespenstern

NP!

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