Pentium 2 address bus size?

kdawg41384

Hi all,

While studying for a+ core hardware test I came across a question on a practice test asking what the size of a pentium 2's address bus is. The technotes on this site say 64 for bus width of a p2, the answer on the test was 32, and after doing some other research I found a couple of sites that said 36 and another that said 64. Can anybody help with some clarification on the size of the address bus for one of these puppys?

Thank you

Kevin

paige1

All Pentiums have 64 bit data buses and 32 bit address buses.

SpiderQueen

I am running into the same confusion about address buses in Pentiums. If I interpret Mike Meyers correctly in his All-In-One Certification guide, all the Pentiums (Pentium, Pentium Pro, Pentiums I, II, III, and 4) have a 32-bit address bus. According to Scott Mueller in Upgrading and Repairing PCs (and also a few other online sources), the Pentium has a 32-bit address bus, but the Pentium Pro, Pentiums I, II, III, and 4 have a 36-bit address bus. Thus, the max addressable memory for the Pentium Pro is 4GB, and then the later Pentiums is 64GB. Which source is correct? I don't know...

fronthome

Yes the newer CPU's have 36 wires but only 32 are used and can only address 4GB of ram according to the sources I have read.

TheShadow

It is more like 36 mod 4. Each address in a intel world is 4 bits or one nibble so address 0 and 1 is a byte, address 2 and 3 is a byte. The pentium addresses on 2 byte boundries so only 32 address lines are needed. This works well with legacy I/O register addressing based on the original 16 bit PC. Intel tech books write this as A35:3 allowing for a 2 to the 36 power address space which is 68,719,476,736 decimal or 64 gig physical address space. Windows is still more or less based on the 386/486 address model hence the 4GB sandbox figure with a few exceptions in the server OS and database code and of course all the new 64 bit code.

Hmmm wait.... OK here is a Pentium 4 spec sheet in PDF format.

ftp://download.intel.com/design/Pentium4/datashts/24919805.pdf

Some where in there should be whats on each pin.

OpenSource

Don't consider this a complete list, but below is an extensive list of processor information I have compiled during my studies. Once again, this list is in the process of being compeleted and I hold liablity for any incorrect information...

However, if you see something incorrect or something you would like to add, please tell me about it. If this is useful to you, let me know. I plan to type up all of my exam notes and I was thinking of posting them online for use by other exam takers.

Processor Specifications:

Zilog Z-80
+ 2MHz/2.5MHz/10MHz
+ Z-80 -> 1MHz
+ Z-80A -> 4MHz
+ CP/M Operating System
+ RadioShack TRS-80 Model #1


4004
+ 108KHz
+ 4-Bit Bus Width
+ 4-Bit Internal Register


6502
+ 8-Bit Bus Width
+ Apple I
+ Apple II (@ 1MHz)
+ Commodore64
+ Vic20


8008
+ 200KHz
+ 8-Bit Bus Width


8080
+ 2MHz
+ 8-Bit Bus Width


8085
+ 5MHz
+ 8-Bit Bus Width


8086
+ 5MHz
+ 20-Bit Addressing
+ 16-Bit Bus Width
+ 16-Bit Internal Register


8088
+ 4.77MHz
+ 8-Bit Bus Width
+ 16-Bit Internal Register
+ 20-Bit Addressing


Altair 8800
+ Unknown


6800/68000
+ Unknown


286
+ 16-Bit Bus Width
+ 16-Bit Internal Register
+ 24-Bit Addressing


386 SX
+ 16-Bit Bus Width
+ 32-Bit Internal Register
+ 24-Bit Addressing


386 SL
+ 16-Bit Bus Width
+ 32-Bit Internal Register


386 DX
+ 32-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Addressing


486
+ 32-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Addressing


486 SX
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 SX2
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 DX
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 SL2
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 DX2
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 DX4
+ 32-Bit Bus Width
+ 32-Bit Internal Register


486 Pentium OD
+ Pentium OverDrive
+ 32-Bit Bus Width
+ 32-Bit Internal Register


487 SX
+ 32-Bit Bus Width
+ 32-Bit Internal Register


AMD 5x86
+ 32-Bit Bus Width
+ 32-Bit Internal Register


Pentium 60/66
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium 75/200
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium MMX
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Addressing


AMD K6
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Addressing


Pentium Pro
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Celeron
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Celeron (Covington)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Celeron A
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium II (Klamath)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Pentium II (Deschutes)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Pentium II PE (Dixon)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Celeron III (Coppermine)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Celeron III (Tualatin)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium III
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Pentium III (Katmai)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Pentium III (Coppermine)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Pentium III (Tualatin)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


AMD Duron
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Addressing


AMD Athlon
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 32-Bit Address Bus


AMD Athlon XP
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Addressing


Celeron 4 (Williamette)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Celeron 4
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium 4
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4 (Williamette)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4A (Northwood)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4B (Northwood)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4C (Northwood)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4EE (Prestonia)
+ Extreme Edition
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Pentium 4E (Prescott)
+ 64-Bit Bus Width
+ 32-Bit Internal Register
+ 36-Bit Address Bus


Celeron D
+ 32-Bit Internal Register Or 64-Bit Internal Register
+ 64-Bit Data Bus Width


Pentium D
+ 32-Bit Internal Register Or 64-Bit Internal Register
+ 64-Bit Data Bus Width


Pentium D (Smithfield)
+ 32-Bit Internal Register Or 64-Bit Internal Register
+ 64-Bit Data Bus Width


Pentium EE (Glenward)
+ 32-Bit Internal Register Or 64-Bit Internal Register
+ 64-Bit Data Bus Width


Pentium M
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium M (Banis)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Pentium M (Dothan)
+ 64-Bit Bus Width
+ 32-Bit Internal Register


Itanium
+ 64-Bit Bus Width
+ 64-Bit Internal Register
+ 44-Bit Addressing


AMD Athlon 64
+ 64-Bit Bus Width
+ 64-Bit Internal Register
+ 40-Bit Addressing


Pentium 4 w/ EM64T
+ 64-Bit Bus Width
+ 64-Bit Internal Register

- Joey

TheShadow

Well OpenSource I think some of the wording on your list is well on the way to confusing you or others. You must understand that there is a difference between 36 bit addressing and a 36 bit address bus; you are mixing the two. One is logical and one is physical!

As I mentioned in my last message if you check the pdf file you will find that there are only 32 physical address lines on even a Pentium 4. A35:3 means that the address lines are logically A0 through A35 which would appear to be 36 lines BUT the lines start at address line 3 so all addresses are mod 4 i.e. we jump in increments of 4 addresses or two bytes. All pentiums not just the pentium 4 as do I believe all Athlons follow this addressing scheme. I would have to drag out my AMD documentation CD from work to check the Athlon/Duron family to be sure. I am on holiday so can't do that. Are you doing this for curiosity, going all the way back to a 4004? I have one of those in the garage somewhere thinking one day it might be worth something.

There are separate internal selectors which determine which byte and nibble that we are pointing to. Once we get to the north bridge it is simplified even more because we always read or write 8 bytes (64 bits) at a time regardless of the address. So the memory control logic is going to do a mod 16 conversion for us at that level to pass data too and from the caching logic unless IORD or IOWR are true. The two signals in the last sentence indicate that we are not after main memory but after something in the I/O subsystem and south bridge enter the equation.

Bottom line every 32 bit Pentium addresses the same way as does every 32 bit Athlon. The cheapy derivatives Celeron and Duron were cannibalized in the caching systems to lower performance and not generally architecture. I will reserve certainty on a couple of early Athlon models in the switch from K5 to K6 due to laziness to check your entire list.

OpenSource

TheShadow wrote:

Well OpenSource I think some of the wording on your list is well on the way to confusing you or others. You must understand that there is a difference between 36 bit addressing and a 36 bit address bus; you are mixing the two. One is logical and one is physical!

Are you doing this for curiosity, going all the way back to a 4004? I have one of those in the garage somewhere thinking one day it might be worth something.

First, as stated:

Once again, this list is in the process of being compeleted and I hold liablity for any incorrect information...

Secondly, I don't quite understand your first statement. Could you elaborate?... The information you provided is mostly correct, though I don't see how it's going to help in this case.

The point of my list was to list the specifications of as many processors as I could think of. Most of the specs are purely for informational purposes, though I know some people might find some of the information useful on exams. Such as questions that pretain to bus width of specific processors.

As for that last statement, yes. It's what I explained above and of course for curiousity. Though I know most of the information I provided on older processors is merely for entertainment purposes as the information is not likely to show up on an exam. And yeah, I have (or used to have) alot of those older processors I listed. Though I know 99% of them got tossed when I moved last year.

- Joey

TheShadow

I'm sorry, I thought that you asked for input. I don't normally hit this forum but it was hot and the beer was cold. I hope it was more than mostly correct since it comes directly from Intels manuals and their engieering briefings that have occured for years at the Intel developers forums. You can find the complete history somehere on intels engineering website. I do not believe the manuals are restricted anymore so you can certainly download them.

My definition of terms has been correct since at least 95 or so. I have done a little non-trivial pentium based circuit design when it was still profitable but I will leave it to you to research an actual motherboard implementation. Maybe the original pentium kit docs from the VLB summer massacre are around. The details on why PCI were in those. Still I am old now and may have made a mistake somewhere.

The original pentium and embedded system version key off this url
http://www.intel.com/design/intarch/mmx/docs_mmx.htm

the pentium pro keys off this archive url
http://www.intel.com/design/archives/processors/pro/

The P6 Pentium II keys off this archive url
http://www.intel.com/design/intarch/pentiumii/docs_pentiumii.htm

The Pentium III keys off this archive url
http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm

The public Pentium 4 docs key off this url
http://www.intel.com/design/Pentium4/documentation.htm#des

My AMD tags are not current and they have updated their web site substantially. I hope that the intel ones are useful for you. As far as the A+ test goes CompTIA's magic number is 64 data and 32 address. Anything else and you will need to battle with the subject matter experts. One or two frequent this forum.

cheers and good luck
oh and check the sticky message from plantwiz on CPU's. There appear to be some good links there

OpenSource

Well, that was a little more information then I needed, but I suppose someone might find it useful. Though I do find it interesting, as I do anything technical. But anyway, yes, I asked for input on anything incorrect or anything that needed to be added.

I originally did not understand what you were really trying to say, or in other words the point of your statements. I understand the technical jargon fine. But upon further review, now that I'm not half asleep, I have a grasp on what you're saying.

That said, if for example a Pentium4 or a PentiumIII have a 32-Bit internal register and a 64-Bit bus width (throughput), why is Intel given 36-Bit addressing when it only really uses 32-Bit??

Is it one of those "well, it's truly 36-Bit, but because of other designs, it can only reach 32-Bit" type things?? ..... Or am I just an idiot??

- Joey

TheShadow

It seems that you are not grasping the implication of MODulus 4. While that is generally a programming term, it is one of the terms that a hardware person must understand.

Consider starting at address 0 in memory we have the values 3f 45 63 e8 address 0 has a 3; address 1 has f; address 2 has 4; address 3 has 5; etc. Now regardless of if a program asks for address 0 or 1 or 2 or 3, all 32 address bits are off. If a program asks for address 4 or 5 or 6 or 7; the 32 bits of address always have a binary value of 1. If a program asks for address 8 or 9, or A or B; the 32 bits of address always have a binary value of 2 and so on. As you can see the first four bits of address are never needed and so therefore are eliminated giving a need for only 32 physical address lines on the address bus but allowing the programmatic logical equivalent of 36 address lines.

The code segment, data segment, stack segment and extra segment allow the same thing to happen on the high bits to allow base 0 relative programming. Variations of these bit manipulation schemes have existed since the 8088 to allow advanced addressing of more data with less bits.

In the Pentium memory control system the first 16 address bits are eliminated reducing the requirement for more pins on the DIMM's and physical chips themselves. There we always jump in increments of 16 addresses which is 16 nibbles or correctly nybbles which is 8 bytes which is 64 data bits. So regardless of where we address in a group of 16 addresses we will always get the same address or MODulus 16 in this case.

I hope this explanation has been clearer. I have worked in the industry for so long that I am often guilty of having jargonitus

TheShadow

I made a serious mistake in my math in the last post. Stupid actually since it is always mod 8 straight from the processor. 386/486 did it mod 4 since they only got 32 bits of data at a time. Same principal except all bits are off for addresses 0, 1, 2, 3, 4, 5, 6, 7. They then have a value of 1 for 8, 9, a, b, c, d, e, f. A value of 2 for addresses, 10, 11, 12, 13, 14, 15, 16, 17. A value of 3 for addresses, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f.

Sorry for the mistake, I had been doing some 16 bit programming and momentarilly warped my mind. I hope I caught it before I did the same to you.

OpenSource

I think I got it, but I'll be sure to read it over again when I'm not so tired. It's a bit confusing though, especially since I haven't done actual programming since high school, years ago...

- Joey