Clock rate on lab router serial connection

ehnde

I just set up - for the first time - a serial connection between my two routers. I used T1 CSU/DSUs in each router with a T1 crossover cable between them. I specifically remember reading that you must set the clock rate on one router or the other, but I didn't do that. It's working anyways.

1721-1#show interface s0
Serial0 is up, line protocol is up
  Hardware is PQUICC with Fractional T1 CSU/DSU
  Internet address is 172.18.21.1/30
  MTU 1500 bytes, BW 1544 Kbit/sec, DLY 20000 usec,
     reliability 255/255, txload 1/255, rxload 1/255
  Encapsulation HDLC, loopback not set
  Keepalive set (10 sec)
  Last input 00:00:09, output 00:00:00, output hang never
  Last clearing of "show interface" counters never
  Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0
  Queueing strategy: fifo
  Output queue: 0/40 (size/max)
  5 minute input rate 0 bits/sec, 0 packets/sec
  5 minute output rate 0 bits/sec, 0 packets/sec
     194 packets input, 13104 bytes, 0 no buffer
     Received 178 broadcasts, 0 runts, 0 giants, 0 throttles
     0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored, 0 abort
     200 packets output, 13605 bytes, 0 underruns
     0 output errors, 0 collisions, 10 interface resets
     0 unknown protocol drops
     0 output buffer failures, 0 output buffers swapped out
     2 carrier transitions
     DCD=up  DSR=up  DTR=up  RTS=up  CTS=up

Is that the wrong command to see which side is DCE and which side is DTE? Why did it automatically go to 1544 Kbit/sec without me fooling with the clocking? Is that standard behavior?

gosh1976

try: show controller s0

and if I'm not mistaken that 1544 Kb has nothing to do with with what the actual bandwidth is - you can change it to whatever you want - you could make it a really high number or really low but it doesn't change what is happening with the real bandwidth of the interface just what is happening with metrics for routing and such

ehnde

That command gives quite a bit of output, but I still don't see the DCE or DTE. A trivial point I suppose....still curious how the clocking is not even needed for this to work.

1721-1#show controllers serial 0
Interface Serial0
Hardware is PowerQUICC MPC860 with Integrated FT1 CSU/DSU module
 TX and RX clocks detected.
idb at 0x83CAAB94, driver data structure at 0x83CB22B8
SCC Registers:
General [GSMR]=0x2:0x00000030, Protocol-specific [PSMR]=0x8
Events [SCCE]=0x0000, Mask [SCCM]=0x001F, Status [SCCS]=0x06
Transmit on Demand [TODR]=0x0, Data Sync [DSR]=0x7E7E
Interrupt Registers:
Config [CICR]=0x00365F80, Pending [CIPR]=0x04008000
Mask   [CIMR]=0x40204000, In-srv  [CISR]=0x00000000
Command register [CR]=0x600
Port A [PADIR]=0x0000, [PAPAR]=0x0903
       [PAODR]=0x0000, [PADAT]=0xE7FE
Port B [PBDIR]=0x0180F, [PBPAR]=0x0E00E
       [PBODR]=0x00000, [PBDAT]=0x3077C
Port C [PCDIR]=0x000, [PCPAR]=0x000
       [PCSO]=0x020,  [PCDAT]=0xFCE, [PCINT]=0x000
Receive Ring
        rmd(FF003030): status 9000 length 1A address 7550464
        rmd(FF00303[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 7550AE4
        rmd(FF003040): status 9000 length 1A address 754A2E4
        rmd(FF00304[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 754A964
        rmd(FF003050): status 9000 length 145 address 754AFE4
        rmd(FF00305[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 754B664
        rmd(FF003060): status 9000 length 1A address 754BCE4
        rmd(FF00306[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 754C364
        rmd(FF003070): status 9000 length 1A address 754C9E4
        rmd(FF00307[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 754D064
        rmd(FF003080): status 9000 length 1A address 754D6E4
        rmd(FF00308[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 145 address 754DD64
        rmd(FF003090): status 9000 length 1A address 754E3E4
        rmd(FF00309[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 9000 length 1A address 754EA64
        rmd(FF0030A0): status 9000 length 1A address 754F0E4
        rmd(FF0030A[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status B000 length 1A address 754F764
Transmit Ring
        tmd(FF0030B0): status 5C00 length 18 address 7558734
        tmd(FF0030B[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 7558AF4
        tmd(FF0030C0): status 5C00 length 143 address 7566C94
        tmd(FF0030C[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 7558EB4
        tmd(FF0030D0): status 5C00 length 18 address 740C614
        tmd(FF0030D[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 740C9D4
        tmd(FF0030E0): status 5C00 length 18 address 740CB14
        tmd(FF0030E[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 740CED4
        tmd(FF0030F0): status 5C00 length 18 address 740DC94
        tmd(FF0030F[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 740DF14
        tmd(FF003100): status 5C00 length 18 address 7557474
        tmd(FF00310[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 143 address 75665B4
        tmd(FF003110): status 5C00 length 18 address 7557834
        tmd(FF00311[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 5C00 length 18 address 7557BF4
        tmd(FF003120): status 5C00 length 18 address 7558374
        tmd(FF00312[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]: status 7C00 length 18 address 7557FB4

tx_limited=0(16)

SCC GENERAL PARAMETER RAM (at 0xFF003C00)
Rx BD Base [RBASE]=0x3030, Fn Code [RFCR]=0x18
Tx BD Base [TBASE]=0x30B0, Fn Code [TFCR]=0x18
Max Rx Buff Len [MRBLR]=1548
Rx State [RSTATE]=0x18008440, BD Ptr [RBPTR]=0x3050
Tx State [TSTATE]=0x18000548, BD Ptr [TBPTR]=0x30F0

SCC HDLC PARAMETER RAM (at 0xFF003C3[IMG]https://us.v-cdn.net/6030959/uploads/images/smilies/icon_cool.gif[/IMG]
CRC Preset [C_PRES]=0xFFFF, Mask [C_MASK]=0xF0B8
Errors: CRC [CRCEC]=0, Aborts [ABTSC]=0, Discards [DISFC]=0
Nonmatch Addr Cntr [NMARC]=0
Retry Count [RETRC]=0
Max Frame Length [MFLR]=1610
Rx Int Threshold [RFTHR]=0, Frame Cnt [RFCNT]=65212
User-defined Address 0000/0000/0000/0000
User-defined Address Mask 0x0000


buffer size 1524

PowerQUICC SCC specific errors:
0 input aborts on receiving flag sequence
0 throttles, 0 enables
0 overruns
0 transmitter underruns
0 transmitter CTS losts

SteveO86

Try

show controllers serial 0 | include dte (or dce)

Piping out the command, adding the include, and the keyword will only give you relevant lines with the word you asked for.

(you can also do the opposite with | exclude xxxx and exclude the out of certain words)

gosh1976

the line that says: TX and RX clocks detected. is what you are looking for.
does it say that on the other side too? I'm guessing it does. Again, I'm just guessing here but you must not have to set the clocking when using that type of interface and a T1 crossover. If on the other hand you were using a DTE/DCE serial cable connection you would see something like DCE V.35, clock rate 56000.

ehnde

SteveO86 wrote: »

Try
show controllers serial 0 | include dte (or dce)

I got no output for either command, but gosh1976's explanation makes sense. Thanks guys.

tiersten

Its a T1 WIC with integrated CSU/DSU. Its always a DTE. The only clocking you can alter is on the CSU/DSU and thats whether to provide the clock that the telco usually does for you. You only turn it on if you're labbing or using a dry loop for some reason. It will work without a clock source for short lengths of cable but you'll get occasional errors when the two ends get out of sync and it won't work if its a long cable.

It says BW 1544 Kbit/sec because thats what a full T1 can do. You need to specify if you want fractional.

Read the manual

gosh1976

I'm curious when setting up the serial interfaces what commands did you use? what does it show for that interface when you do a show run?

I'm not sure why you wouldn't have to do a command like service-module T1 Clock Source Line or or some other command and i hope someone explains.

gosh1976

here is a quick explanation on the bandwidth command Clarifying the Cisco IOS bandwidth command

ehnde

I want to make sure I understand...the connection will work with occassional errors without setting the clock rate. But in a lab environment working between two CSU/DSU interfaces you can set the clock rate on one side and there would be no errors?

At least I understand the part about DTE on both sides, hence the need for a crossover.

tiersten

You're trying to follow instructions for a plain sync serial connection and applying it to a T1 WIC with integrated CSU/DSU when you can't do that.

The internal sync serial link between the T1 controller and the CSU/DSU on the WIC is where you would have set "clock rate" but as its integrated, Cisco handle all that for you and you don't care which end is DCE or DTE. It just does it automatically as you're never changing one without the other also changing.

The T1 CSU/DSU expects there to be a clock on the leased line that the telco generates. The default is "clock source line" for this WICs CSU/DSU which tells it to expect a clock on the line. One end of your lab connection will need to be changed to "clock source internal" so it will generate the clock itself.

gosh1976

Using the Cisco 2524-2525 Back-to-Back [Cisco 2500 Series Routers] - Cisco Systems

So one side should be set to clock source line and the other to clock source internal? I followed that link from the page tiersten linked to so I assume it applies.

gosh1976

apparently I type slow

tiersten

gosh1976 wrote: »

So one side should be set to clock source line and the other to clock source internal?

If you're using WIC-1DSU-T1s then yes. One side will default to "clock source line" and the other side should be set to "clock source internal". It will sort of work without you setting this but it won't be reliable and may refuse to work at all if it is a long wire.

tiersten

WIC-1DSU-T1s are an acceptable replacement for WIC-1T/WIC-2T cards and some people prefer them due to the neater and easier to make cabling. The difference is the whole DCE/DTE issue and how you handle clocking. You need to be aware of this when buying WIC-1DSU-T1s and using labs which were written for regular sync serial interfaces.

ehnde

1721-1#show service-module s0 | include clock

I got a little more info from this command in regards to clocking, both ends say pretty much the same thing. Clock source line. But tiersten's explanation made sense, time to move on to more labbing