Exclusively for TechExams members for Infosec Boot Camps starting before April 30, 2026
Interface Serial0/0 R2#show controllers s0/0 Hardware is GT96K [b]DCE 530, clock rate 2000000[/b] idb at 0x66547418, driver data structure at 0x6654EB24 wic_info 0x6654F150 Physical Port 1, SCC Num 1 MPSC Registers: ***output omitted***
R2#show int s0/0 Serial0/0 is up, line protocol is down Hardware is GT96K Serial MTU 1500 bytes, BW 1544 Kbit/sec, DLY 20000 usec, reliability 255/255, txload 1/255, rxload 1/255 [b]Encapsulation PPP[/b], LCP Listen, loopback not set
Exclusively for TechExam members. Applies to boot camps starting before April 30, 2026.